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research-article

Optimal Design of Three-Dimensional Heat Flow Structures for Power Electronics Applications

[+] Author and Article Information
Ercan Dede

Electronics Research Department, Toyota Research Institute of North America, 1555 Woodridge Ave., Ann Arbor, Michigan 48105
eric.dede@toyota.com

Yanghe Liu

Electronics Research Department, Toyota Research Institute of North America, 1555 Woodridge Ave., Ann Arbor, Michigan 48105
yanghe.liu@toyota.com

Shailesh Joshi

Electronics Research Department, Toyota Research Institute of North America, 1555 Woodridge Ave., Ann Arbor, Michigan 48105
shailesh.joshi@toyota.com

Feng Zhou

Electronics Research Department, Toyota Research Institute of North America, 1555 Woodridge Ave., Ann Arbor, Michigan 48105
feng.zhou@toyota.com

Danny Lohan

Electronics Research Department, Toyota Research Institute of North America, 1555 Woodridge Ave., Ann Arbor, Michigan 48105
danloh91@gmail.com

Jong-Won Shin

Electronics Research Department, Toyota Research Institute of North America, 1555 Woodridge Ave., Ann Arbor, Michigan 48105
jongwon.shin@toyota.com

1Corresponding author.

ASME doi:10.1115/1.4041440 History: Received January 02, 2018; Revised August 31, 2018

Abstract

Design optimization of a three-dimensional (3-D) heat flow structure for power electronics gate drive circuit thermal management is described. Optimization methods are described in the creation of several structural concepts targeted towards simultaneous temperature reduction of multiple gate drive integrated circuit (IC) devices. Each heat flow path concept is intended for seamless integration based on power electronics packaging space constraints, while maintaining required electrical isolation. The design synthesis and fabrication of a select concept prototype is presented along with the development of an experimental test bench for thermal performance characterization. Experimental results indicate a significant 45 degree C maximum temperature reduction for the gate drive IC devices in a laboratory environment, which translates to an estimated 41 degree C maximum temperature reduction under high temperature (~100 degree C) ambient conditions. The technical approach and design strategy is applicable to future wide band-gap (WBG) electronics packaging applications, where enhanced 3-D thermal routing is expected to be critical to maximizing volumetric power density.

Copyright (c) 2018 by ASME
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