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Research Papers

Optimal Design of Three-Dimensional Heat Flow Structures for Power Electronics Applications

[+] Author and Article Information
Ercan M. Dede

Electronics Research Department,
Toyota Research Institute of North America,
1555 Woodridge Ave,
Ann Arbor, MI 48105
e-mail: eric.dede@toyota.com

Yanghe Liu, Shailesh N. Joshi, Feng Zhou, Danny J. Lohan, Jong-Won Shin

Electronics Research Department,
Toyota Research Institute of North America,
1555 Woodridge Ave,
Ann Arbor, MI 48105

1Corresponding author.

Contributed by the Heat Transfer Division of ASME for publication in the JOURNAL OF THERMAL SCIENCE AND ENGINEERING APPLICATIONS. Manuscript received January 2, 2018; final manuscript received August 31, 2018; published online December 5, 2018. Assoc. Editor: Gamal Refaie-Ahmed.

J. Thermal Sci. Eng. Appl 11(2), 021011 (Dec 05, 2018) (12 pages) Paper No: TSEA-18-1001; doi: 10.1115/1.4041440 History: Received January 02, 2018; Revised August 31, 2018

Design optimization of a three-dimensional (3D) heat flow structure for power electronics gate drive circuit thermal management is described. Optimization methods are described in the creation of several structural concepts targeted toward simultaneous temperature reduction of multiple gate drive integrated circuit (IC) devices. Each heat flow path concept is intended for seamless integration based on power electronics packaging space constraints, while maintaining required electrical isolation. The design synthesis and fabrication of a select concept prototype is presented along with the development of an experimental test bench for thermal performance characterization. Experimental results indicate a significant 45 ∘C maximum temperature reduction for the gate drive IC devices in a laboratory environment, which translates to an estimated 41 °C maximum temperature reduction under high temperature (∼100 °C) ambient conditions. The technical approach and design strategy are applicable to future wide band-gap (WBG) electronics packaging applications, where enhanced 3D thermal routing is expected to be critical to maximizing volumetric power density.

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Figures

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Fig. 1

Typical configuration of gate driver

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Fig. 2

Power control unit downsizing image and goal. (Reprinted with permission from Hamada et al. [28]. Copyright 2015 by IEEE).

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Fig. 3

Cutaway view of a representative PCU; adapted with permission from Ref. [29]

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Fig. 4

Solid model geometry for computational analysis: (a) isometric view, (b) top view with PCB transparent for clarity — red-dashed boxes indicate gate drive IC device locations, and (c) section view of stacked cooler with control PCB directly above

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Fig. 5

Thermal contour results for baseline numerical model: (a) control PCB with upper case frame shown transparent and inner power card stack plus cooler hidden, for clarity, and (b) upper case frame only

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Fig. 6

Cross section schematic of design region and concept for 3D heat flow structure

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Fig. 7

Loads and BCs for 2D optimization study

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Fig. 8

Pareto front of material fraction design sensitivity. Note: for inset images, dark regions = thermally conductive (i.e., solid) material; light regions = nonthermally conductive material (i.e., void).

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Fig. 9

Extracted air volume 3D design domain

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Fig. 10

Three-dimensional heat flow structure optimization results. Note: dark regions = thermally conductive (i.e., solid) material; light regions = nonthermally conductive material (i.e., void).

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Fig. 11

Design synthesis process from optimization result to rapid prototype

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Fig. 12

Thermal contour results comparing performance of 3D heat flow structure in as-optimized, (a), versus monolithic (b), form

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Fig. 13

Experimental setup: (a) prototype Al 3D heat flow structure; (b) control PCB bottom side view—red circled IC devices are powered, and (c) PCB mounted into upper case frame with overlaid view of TEC plus 3D heat flow structure assembly including TIMs (mounted between PCB and case)

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Fig. 14

Experimental results for IC device maximum, minimum, and average temperature measurements

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