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Research Papers

Onboard Device Encapsulation With Two-Phase Cooling

[+] Author and Article Information
S. J. Young

General Dynamics Mission Systems,
Bloomington, MN 55431

D. Janssen, E. A. Wenzel, B. M. Shadakofsky

Department of Mechanical Engineering,
University of Minnesota,
Minneapolis, MN 55455

F. A. Kulacki

Department of Mechanical Engineering,
University of Minnesota,
Minneapolis, MN 55455
e-mail: kulacki@me.umn.edu

1Corresponding author.

Contributed by the Heat Transfer Division of ASME for publication in the JOURNAL OF THERMAL SCIENCE AND ENGINEERING APPLICATIONS. Manuscript received August 4, 2016; final manuscript received May 19, 2017; published online August 29, 2017. Assoc. Editor: Gamal Refaie-Ahmed.

J. Thermal Sci. Eng. Appl 10(2), 021002 (Aug 29, 2017) (13 pages) Paper No: TSEA-16-1217; doi: 10.1115/1.4037130 History: Received August 04, 2016; Revised May 19, 2017

Onboard liquid cooling of electronic devices is demonstrated with liquid delivered externally to the point of heat removal through a conformal encapsulation. The encapsulation creates a flat microgap above the integrated circuit (IC) and delivers a uniform inlet coolant flow over the device. The coolant is Novec™ 7200, and the electronics are simulated with a resistance heater on a 1:1 scale. Thermal performance is demonstrated at power densities of ∼1 kW/cm3 in the microgap. Parameters investigated are pressure drop, average device temperature, heat transfer coefficient, and coefficient of performance (COP). Nusselt numbers for gap sizes of 0.25, 0.5, and 0.75 mm are reduced to a dimensionless correlation. With low coolant inlet subcooling, two-phase heat transfer is seen at all mass flows. Device temperatures reach 95 °C for power dissipation of 50–80 W (0.67–1.08 kW/cm3) depending on coolant flow for a gap of 0.5 mm. Coefficients of performance of ∼100 to 70,000 are determined via measured pressure drop and demonstrate a low pumping penalty at the device level within the range of power and coolant flow considered. The encapsulation with microgap flow boiling provides a means for use of higher power central processing unit and graphics processing unit devices and thereby enables higher computing performance, for example, in embedded airborne computers.

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Figures

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Fig. 1

Conceptual conformal encapsulation at the device level with coolant flow

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Fig. 2

Heat transfer coefficients with flow field visualization in flow boiling in a microgap of 300 and 1000 μm [18]. qeff″  = wall heat flux.

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Fig. 3

Overall heat transfer coefficient versus exit quality with regression fit [21]. Hollow data points are for a multiple chip pairs [20].

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Fig. 4

Nusselt numbers in terms of Reynolds and boiling numbers for d = 0.36 mm and three in-line pairs of heaters [19] (solid points). Results for a single pair of heaters [20] are shown for comparison.

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Fig. 5

(a) Computer-aided design rendering of the encapsulation showing smooth roof line transitions. (b) Section A-A view of the inlet port with smooth transition to 1 mm DIA in plane flow to inlet manifold. (c) Detail of channelized inlet manifold. Bypass flow blocker is at the upper right.

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Fig. 6

Manifold configurations (CF) with flow blockers and flow directions shown. (a) CF-1: channelized inlet and outlet with 80% bypass area blocked. (b) CF-2: channelized inlet and open outlet with 80% bypass area blocked. (c) CF-3: channelized inlet and open outlet with 33% bypass area blocked. (d) CF-4: Open inlet and outlet with 80% bypass are blocked.

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Fig. 7

Flow management system

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Fig. 8

Chip temperature with subcooled inlet flow. d = 0.5 mm. Manifold configuration CF-1: channelized inlet and outlet manifolds. Q is coolant volume flow in L/min. Bypass area flow blocking = 80%.

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Fig. 9

Chip temperature with subcooled inlet flow. CF-2: channelized inlet and open outlet manifolds. Q is the coolant volume flow in L/min. Bypass flow blocking = 80%.

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Fig. 10

Chip temperature with subcooled inlet flow. d = 0.5 mm. Manifold configuration CF-3: channelized inlet and open outlet manifolds. Q is coolant volume flow in L/min. Bypass area flow blocking = 33%.

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Fig. 11

Chip temperatures with subcooled inlet flow. d = 0.5 mm. Manifold configuration CF-4: open inlet and outlet manifolds. Q is coolant volume flow in L/min. Bypass area flow blocking = 80%.

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Fig. 12

Heat transfer coefficients with subcooled inlet flow. d = 0.5 mm. Manifold configuration CF-1: channelized inlet and outlet manifolds. Q is coolant volume flow in L/min. Bypass area flow blocking = 80%.

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Fig. 13

Heat transfer coefficients with subcooled inlet flow. d = 0.5 mm. Manifold configuration CF-2: channelized inlet and open outlet manifolds. Q is coolant volume flow in L/min. Bypass area flow blocking = 80%.

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Fig. 14

Heat transfer coefficients with subcooled inlet flow. d = 0.5 mm. Manifold configuration CF-3: channelized inlet and open outlet manifolds. Q is coolant volume flow in L/min. Bypass area flow blocking = 33%.

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Fig. 15

Heat transfer coefficients with subcooled inlet flow. d = 0.5 mm. Manifold configuration. CF-4: open inlet and open outlet manifolds. Q is coolant volume flow in L/min. Bypass area flow blocking = 80%.

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Fig. 16

Chip temperature for d = 0.75 mm. Manifold configuration CF-1: channelized inlet and outlet. Q is volume flow in L/min. Bypass area flow blocking = 80%. Last entry in each legend corresponds to d = 0.5 mm.

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Fig. 17

Chip temperature for d = 0.25 mm. Manifold configuration CF-1: channelized inlet and outlet. Q is volume flow in L/min. Bypass area flow blocking = 80%. Last entry in each legend corresponds to d = 0.5 mm.

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Fig. 18

Power input versus chip temperature. CF-1. Ti = 25 °C.

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Fig. 19

Reduced Nusselt number versus heater chip temperature. d = 0.5 mm. Manifold configurations CF-1 and CF-4. Ti = 25 °C. G = 100–500 kg/m2 s.

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Fig. 20

Heat transfer coefficients, pressure drop and COP. d = 0.5 mm. Manifold configurations CF-1, CF-2, CF-3, and CF-4. Ti = 25 °C.

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