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# Effects of Trace Layers and Joule Heating on the Temperature Distribution of Printed Circuit Boards: A Computational Study

[+] Author and Article Information
M. Baris Dogruoz

ICE Division, Ansys Inc., 2700 Via Fortuna Drive, Suite 301, Austin, TX 78746mbd@fluent.com

Manoj K. Nagulapally

ICE Division, Ansys Inc., 2700 Via Fortuna Drive, Suite 301, Austin, TX 78746mn@fluent.com

J. Thermal Sci. Eng. Appl 1(2), 022003 (Nov 12, 2009) (10 pages) doi:10.1115/1.4000286 History: Received March 25, 2009; Revised August 28, 2009; Published November 12, 2009; Online November 12, 2009

## Abstract

A printed circuit board (PCB) is generally a multilayered board made of dielectric material and several layers of traces and vias. Performing detailed system-level computational fluid dynamics (CFD) simulations of PCBs including meshed trace and via geometries for each of the layers is impractical. In the present approach, the effects of the trace and via geometry are accurately modeled in the physical model by importing electronics computer aided-design data consisting of the trace and via layout of the board and computing locally varying orthotropic conductivity ($kx$, $ky$, and $kz$) on the printed circuit board using a background mesh. The spatially varying orthotropic conductivity is then mapped from the background mesh to the CFD mesh and used in a system-level simulation of the PCB with a minimal increase in the overall computational cost. On the other hand, as PCB component densities increase, the current densities increase thereby leading to regions of hot spots due to Joule heating. Hence, it is essential that the computational heat transfer simulations account for the heating due to the high current carrying traces. In order to accurately model the Joule heating of traces and vias, it is of essence to solve for the conservation of current in each of these traces. In this study, the effects of both trace layer nonhomogeneity and Joule heating are examined on a sample PCB with several components attached to it. The results are then compared with those from the conventional modeling techniques. It is demonstrated that there is considerable difference in the location of the hot spots and temperature values between two different methods.

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## Figures

Figure 1

PCB geometry

Figure 2

(a) Top: power budget. (b) Bottom: trace map.

Figure 3

The trace layout and the thermal conductivity map for Layer 1 (left column) and Layer 3 (right column)

Figure 4

The trace layout and the thermal conductivity map for Layer 5 (left column) and Layer 7 (right column)

Figure 5

Comparison of the temperature contours on the top (left) and bottom (right) sides of the PCB with two different conductivity mapping techniques

Figure 6

The temperature contours on the top (left-top) and the bottom (left-bottom) sides of the PCB and the trace A (right) at Iin=25 A (trace image not to scale with the PCB images)

Figure 7

The temperature contours on the top (left-top) and the bottom (left-bottom) sides of the PCB and the trace B (right) at Iin=25 A (trace image not to scale with the PCB images)

Figure 8

The temperature contours on the top (left-top) and the bottom (left-bottom) sides of the PCB and the trace C (right) at Iin=25 A (trace image not to scale with the PCB images)

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