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Research Papers

Optimal Design of Three-Dimensional Heat Flow Structures for Power Electronics Applications PUBLIC ACCESS

[+] Author and Article Information
Ercan M. Dede

Electronics Research Department,
Toyota Research Institute of North America,
1555 Woodridge Ave,
Ann Arbor, MI 48105
e-mail: eric.dede@toyota.com

Yanghe Liu, Shailesh N. Joshi, Feng Zhou, Danny J. Lohan, Jong-Won Shin

Electronics Research Department,
Toyota Research Institute of North America,
1555 Woodridge Ave,
Ann Arbor, MI 48105

1Corresponding author.

Contributed by the Heat Transfer Division of ASME for publication in the JOURNAL OF THERMAL SCIENCE AND ENGINEERING APPLICATIONS. Manuscript received January 2, 2018; final manuscript received August 31, 2018; published online December 5, 2018. Assoc. Editor: Gamal Refaie-Ahmed.

J. Thermal Sci. Eng. Appl 11(2), 021011 (Dec 05, 2018) (12 pages) Paper No: TSEA-18-1001; doi: 10.1115/1.4041440 History: Received January 02, 2018; Revised August 31, 2018

Design optimization of a three-dimensional (3D) heat flow structure for power electronics gate drive circuit thermal management is described. Optimization methods are described in the creation of several structural concepts targeted toward simultaneous temperature reduction of multiple gate drive integrated circuit (IC) devices. Each heat flow path concept is intended for seamless integration based on power electronics packaging space constraints, while maintaining required electrical isolation. The design synthesis and fabrication of a select concept prototype is presented along with the development of an experimental test bench for thermal performance characterization. Experimental results indicate a significant 45 ∘C maximum temperature reduction for the gate drive IC devices in a laboratory environment, which translates to an estimated 41 °C maximum temperature reduction under high temperature (∼100 °C) ambient conditions. The technical approach and design strategy are applicable to future wide band-gap (WBG) electronics packaging applications, where enhanced 3D thermal routing is expected to be critical to maximizing volumetric power density.

FIGURES IN THIS ARTICLE
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Continual miniaturization for increased power density is a recurring theme for advanced power electronics found in next-generation hybrid and electric vehicles. Representative examples from the literature [13] highlight a steady progression of the industry state of the art with a roughly 10–40% decrease in volume over successive generations of a typical power electronics assembly. This ceaseless decrease in size has led to significant thermal management challenges as power density correspondingly increases [4].

While high-performance heat spreading [5], single-phase liquid cooling [68], and two-phase cooling [9,10] for large-area (on the order of ∼ 1 cm2) power semiconductor devices are traditional advanced research focus areas for energy conversion applications, thermal management of associated control electronics and passive circuit elements is increasingly relevant for high volumetric power density designs [11]. For automotive power electronics, situations involving increased power density in combination with high ambient temperatures (upward of 200 °C) are emerging [12], and these cases require multiple cooling strategies for the power semiconductors, control (e.g., gate drive) electronics, and associated passives such as DC-link capacitors [13]. Specific to this work, the role of the gate drive IC device is to provide a certain gate current to switch the power semiconductor device to a low impedance state. Although the heat dissipation of a gate drive IC is small relative to a power semiconductor, such an IC device is traditionally passively cooled and is surface mounted on a printed circuit board (PCB).

For a surface mounted device (SMD) on a PCB, many approaches exist for thermal management of standard integrated circuit (IC) packages. For example, a thermal spreader or cap may be attached to the SMD followed by a heat sink that is thermally connected by way of a thermal interface material (TIM) [14]. The gate driver in Ref. [15] is a typical example of an IC package with an exposed metal back intended for such applications. Alternatively, forced convection via guided air flow over the PCB may be utilized [16], thermal coupling to components with high thermal conductivity, and large surface area can be leveraged, or copper (Cu) filling may be used in all available layers/regions of the PCB for enhanced heat spreading [11]. Other interesting three-dimensional (3D) packaging solutions for high board stacking density consider multiple layers in a “power sandwich” configuration for multiple (e.g., mechanical, thermal, electrical) functions [17]. Furthermore, conductive heat transfer through thick Cu PCBs [16] or heat-pipe-assisted Cu heat spreaders [18] to direct heat flow in three dimensions to a liquid-cooled heat sink or chassis is proposed for power-dense applications including microservers. This latter work provides a clear image for the manner in which an effectively designed 3D heat flow path that combines multiple heat transfer mechanisms enables high power density design.

From a circuit perspective, inefficiency of gate driver hard switching is the root cause of its heat dissipation. A conventional gate driver IC generally contains a totem pole or a pair of switches, as shown in Fig. 1. Hard switching of this pair of switches contributes most to the gate drive IC device power loss. Neglecting the quiescent power consumption of the logic components and conduction loss of the pair of switches, gate driver loss, Pgd, is defined, per [19], as Display Formula

(1)Pgd=Cg×Vdd2×f

where Cg is the input gate capacitance of the power semiconductor, Vdd is the difference between the on-state and off-stage gate terminal voltage, and f is the switching frequency. Development of next-generation wide band-gap (WBG) power semiconductor devices such as silicon carbide (SiC) pushes Vdd higher than the case for silicon (Si) power devices (for example, Vdd ∼ 15–20 V for a Si IGBT versus Vdd ∼ 20–25 V for a SiC metal-oxide-semiconductor field-effect transistor (MOSFET)) with higher f. This increases Pgd for the gate drive IC device, per Eq. (1), which in turn calls for careful thermal management.

Resonant gate driving technology has been spotlighted to improve driving power devices. The technology is promising in reducing the heat dissipation of the gate drive IC [2022], as well as in increasing the switching speed [23]. This technology revises the totem-pole circuit structure so that the pair of switches operates with soft switching. However, inclusion of bulky passive components, such as resonant inductors, poses a challenge for compact packaging. Another approach to suppress the heat dissipation of the gate driver is to employ WBG material for the totem-pole switches to reduce their conduction loss [24,25]. The low on-state resistance contributes to reduction of the conduction loss, although increased system cost raises another challenge. Regardless of a circuit-level solution, all active power devices still dissipate heat, and in combination with reduced package form factors and high ambient temperatures active devices will still require effective heat removal strategies.

Thus, the contribution of this work is to present a broadly applicable and detailed design optimization and synthesis methodology for the generation of unique 3D thermal routing or heat flow structures for power electronics auxiliary PCBs with SMDs in support of compact high power density design under harsh environments. A background of the thermal management challenge is provided first in Sec. 2 including a baseline thermal analysis of the case at hand and a detailed description of the technology down-selection process plus selected technical approach. Implementation of optimization methods [26,27] in both two dimensions (2D) and 3D for exploration of the design space and structural concept generation is described in Sec. 3. This portion of the paper includes details of the optimization process, design concept results, synthesis and fabrication of a selected novel prototype structure, and numerical modeling to estimate the effect of the 3D heat flow structure on thermal performance. In Sec. 4, experimental verification and additional validation by simulation of the thermal performance of the selected prototype design is explained. Conclusions then follow in Sec. 5.

A transparent isometric view of a typical vehicle power control unit (PCU) including downsizing image, adapted from Ref. [28], is shown in Fig. 2. As discussed by Hamada et al. [28], the use of emerging WBG, e.g. SiC, power devices is anticipated to enable up to an 80% reduction in overall PCU volume leading to a significant increase in power density. Future power module WBG power semiconductors in a typical PCU are actively cooled [1,3] and may be capable of high temperature, i.e., ∼200 °C operation, in the future [28]. However, the co-location of silicon (Si) and SiC in the same assembly poses challenges due to different temperature limitations for each semiconductor material, and common solders, substrates, and passive (e.g., magnetic) devices are further limited in their high temperature operation. For example, associated control circuitry is often passively cooled leading to thermal management challenges as Si gate drive IC device temperatures reach a general 150 °C limit and FR-4 PCB temperatures approach a typical material glass transition temperature range of 120–180 °C. A cutaway view of a representative PCU is shown in Fig. 3, from Ref. [29], with the control circuit PCB at the uppermost level and a vertically oriented stacked power card-based power module with interleaved double-side liquid cooling directly below. At a high level, the assembly in Fig. 3 illustrates the 3D trend of current and future power electronics packaging strategies across a variety of applications.

Numerical Analysis.

To more fully illustrate the thermal challenges arising from high power density 3D design coupled with the harsh under-hood vehicle environment, a heat transfer analysis of the upper case frame, stacked power module plus cooler, and gate drive portion of the control PCB of a representative PCU is carried out with commercial finite element software [30]. The primary heat loads in the system are taken as the gate drive IC devices (as opposed to other PCB components such as the board power supply or logic IC) based on independent thermal imaging of the circuit under actual system operation.

The governing equation for steady-state heat conduction in Cartesian component form in a 3D domain, Ω, is Display Formula

(2)Q=xi(kijTxj)inΩ

where kij are the Cartesian components of the thermal conductivity tensor, T is the temperature state variable, and Q is the volumetric heat generated inside the domain [31]. Summation on repeated subscripts is assumed, where i and j are summed over the range of i, j = 1, 2, 3. The boundary conditions (BCs) are given by, Display Formula

(3)T=f(T)onΓT,and
Display Formula
(4)(kijTxj)ni=qa+qconΓq

where the function, f(T), specifies the required temperature condition on the boundary ΓT, qa is an applied heat flux on the boundary Γq, and qc = h(TTo) is the convective flux on Γq, which is a function of the surface convection coefficient, h, at a reference temperature, To.

Here, assumptions are made to reduce the physical complexity of the model shown in Fig. 4. Specifically, the lower portion, reactor coil, capacitors, lower case frame plus DC/DC converter, and assembly cover are not modeled since they are not considered part of the primary conduction heat transfer path for the gate drive IC PCB; refer to Kitazawa et al. [3] for explanatory details of the various components. Table 1 provides a summary of the assumed model loads, BCs, and material properties for the model. Based on separate system level test data, the power loss and ambient/fixed temperature values in Table 1 are justified as representative PCU device power loss and under hood temperature boundary conditions for estimating the effect of proposed thermal management solutions. Observe in Fig. 4(c) that the power cards are liquid cooled at a fluid inlet temperature of 65 °C. However, the gate drive circuit board does not connect to this liquid cooler and thus is passively air cooled. Accordingly, the assumed convection coefficients in Table 1 are typical for natural convection [32].

In lieu of a computationally expensive conjugate heat transfer analysis, a simplified fixed temperature boundary condition is assumed and applied to the cooler including fluid inlet and outlet ports. Volumetric heat generation, Q, is applied to each gate drive IC device and power card structure, per Table 1. Buoyancy effects are neglected, and a fixed free surface convection coefficient, h, boundary condition is assigned on both the exterior and interior surfaces of the upper case frame, at respective reference temperatures. Thermal radiation is neglected. Observe that the most thermally impactful harsh environment boundary conditions in this table are these relatively high ambient under hood reference temperatures inside and outside of the case. For the control PCB, the in-plane and cross-plane effective thermal conductivity, k, of Cu-filled and non-Cu regions is calculated using composite slab theory [33] based on the detailed board material and layer stack up. Each gate drive IC device is further modeled as a two layer structure with a thermal conductivity consistent with epoxy, k = 0.2 W/mK, at the top layer and a higher thermal conductivity, k = 150 W/mK, for the bottom layer of the IC device. Standard aluminum (Al) properties are given for the upper case frame. A mesh refinement study is performed to assure grid independence with the final mesh comprising approximately 4.0 × 105 tetrahedral finite elements.

The thermal contour results of the baseline numerical analysis for the control PCB are shown in Fig. 5(a), where a maximum IC device temperature, TICmax= 162 °C, is observed. The minimum device temperature, TICmin, from the model is 125 °C for an overall device temperature range, Tr=TICmaxTICmin, of 37 °C; note that device temperature range, Tr, may be related to system performance, with a lower range preferred. Further, observe in Fig. 5(b) that the temperature variation of the upper case frame is approximately 12.5 °C with the lowest temperatures, close to ∼ 65 °C, corresponding to the direct contact locations for the liquid cooler.

Technology Down-Selection and Approach.

A first possible solution to the thermal challenge of lowering the gate drive IC device maximum temperature is increasing the junction size of the totem-pole switches in Fig. 1. This strategy lowers on-state resistance and hence reduces power loss. Generally, the junction resistance, r, of a MOSFET is determined by channel length, L, and width, W, per [34], as Display Formula

(5)r=[KWL(VgsVt)]1

In Eq. (5), K is a constant, units: (Ohm V)−1, determined by the semiconductor material characteristic and process technology, Vgs is the gate-source voltage, and Vt is the threshold voltage. Increasing the junction size reduces the resistance, r, because it is equivalent to increasing the channel width, W. However, a larger junction area implies potentially lower reliability, increased cost, and a bulky IC size that occupies a larger area on the PCB.

A second technical approach is to counteract the high ambient air temperature environment by actively supplying cold air to the upper portion of the electronics enclosure and actively air cool the gate drive circuit PCB. Unfortunately, a major drawback to this approach is the added complexity of piping cool air to the compactly packaged enclosure under the hood and the potential reliability and fouling issues associated with the use of a fan and associated air coolant, respectively.

The addition of a Cu core/inlay or optimizing the anisotropic thermal conductivity of the PCB using customized thermal traces [35] is a third possible design solution for passive thermal (i.e., heat flux) routing. However, an effective heat sinking location is still required, and special consideration must be given to maintaining electrical isolation between high voltage and low voltage regions of the circuit while achieving high thermal performance, e.g., >25 ∘C IC device temperature reduction.

A fourth solution is also considered where thermally conductive material may be used to connect the gate drive IC devices to the liquid cooler located in the PCU. This is an elegant passive solution, which can replace existing air volume in the PCU with a thermally conductive, yet electrically insulating, heat flow structure. Using low thermal resistance heat conduction between the gate drive IC device heat sources and a thermal ground is a potentially highly effective way to obtain high heat transfer with minimal added system complexity, and these merits are transferable to future WBG systems as well.

Based on the relative advantages and disadvantages of the four technologies discussed qualitatively in the proceeding paragraphs, the different options have been scored in Table 2.

Due to the presence of the liquid cooler, the heat flow structure with thermal grounding concept has clear advantages over the remaining concepts. Thus, the technical approach of optimizing a 3D heat flow path is adopted to thermally couple the gate drive IC devices to the cold liquid cooler or upper case frame, Fig. 5(b), with two interposed TIMs. Figure 6 shows a basic cross section schematic of this concept and associated design region. In this figure, TIM1 provides for thermal communication plus electrical isolation between the gate drive IC devices and the heat flow structure, while TIM2 serves to facilitate heat transfer between the heat flow structure and the cooler or upper case frame. In addition to significantly reducing the gate drive IC device temperatures by at least 25 °C, a secondary goal is to design the 3D heat flow path within the existing “dead space” air gap or empty volume of the electronics package assembly.

To design the conductive heat flow path, a structural topology optimization approach based on gradient-based optimization techniques [26] is used to maximize heat transfer while reducing component weight. Steady-state heat conduction in an isotropic solid, Eq. (2), is assumed for the design domain, where the thermal conductivity, k, is equal in all directions. In the optimization routine, the thermal conductivity material physical parameter is interpolated between a minimum and maximum value using the solid isotropic material with penalization scheme Display Formula

(6)k=(0.001+.999γp)ko

where ko is a reference (solid material) thermal conductivity value, γ is the design parameter, and an interpolation penalization parameter value, p = 3, is assumed [26]. In Eq. (6), k → 0.001 ko represents air (void), while kko represents thermally conductive (solid) material.

Thus, the optimization problem statement is formalized as the minimization of the average temperature, T¯, in the 3D design domain subject to an upper bound material resource (i.e., volume) constraint, vo. A Helmholtz filtering routing utilizing a filter radius, rf, for mesh independence and to enforce a minimum structural length scale is used. Thus, the problem statement is

FindγMinimizeT¯SubjecttoEqs.(2)(4)vvo00γ1GivenEq.(6);

refer to Refs. [26,27], and [36] for extensive details and examples. The optimization process is implemented in a finite element software package with a sparse nonlinear optimizer (SNOPT) [37]. The globally convergent method of moving asymptotes optimizer, a well-performing algorithm for topology optimization [38], is additionally explored.

Two-Dimensional Optimization and Results.

Prior to optimizing the full 3D structure, a reduced computational cost 2D exploration of the design space using topology optimization is presented to understand interrelationships between the general size (i.e., volume) of the heat flow structure and its effect on heat source temperature reduction. Consider the x-z plane (refer to Fig. 5) on which the gate drive IC devices reside, as presented in Fig. 7. The computational model is initialized using the parameters in Table 1, where the device heat flux is input to the red-colored device location regions, the exterior boundary is adiabatic, and the temperature is fixed at the dotted blue line, where the interface to the PCU liquid cooler resides. To gauge the sensitivity of heat flow structure performance to the material volume fraction constraint, a pareto-front of optimal designs is obtained using the SNOPT optimizer, Fig. 8. The temperature axis is normalized such that the highest temperature is unity and lowest temperature is zero.

Observe in Fig. 8 that increasing the material fraction past 20% has diminishing returns for increased thermal performance. By analyzing the topological structures, it is deduced that the optimizer places conductive paths connecting sink to source in the most efficient means possible [36]. Increasing the material fraction has diminishing benefit since the conductive paths between sink and source have already been established using less material. The diminishing return with increased material is a characteristic of using a fixed temperature boundary condition near the heat sources. This characteristic is not typical in systems where convection replaces the fixed temperature condition. Acknowledging that the optimizer needs a sufficient amount of material to connect the heat sources to the heat sink, a material volume fraction of ∼20% is selected for a full 3D optimization to understand out-of-plane structural design features.

Three-Dimensional Optimization and Results.

The previously presented 2D optimization is useful as a computationally inexpensive means to calibrate design settings. To obtain a solution that is meaningful in implementation, a 3D optimization must be performed. 3D topology optimization examples available in the literature cover a range of applications including the design of thermoelectric coolers (TECs) for downhole electronics [39], the design of air-cooled heat sinks subjected to impinging flows [40], and the design of heat sinks under natural convection [41]. As described in these prior works, implementation in 3D is computational intensive, and this present study is unique in its application of 3D topological structural design to conductive heat flow structures for power electronics gate drive IC device temperature control.

To facilitate the optimization study, the air volume, or 3D design domain, is extracted from the previously introduced solid model geometry, as shown in Fig. 9. This design domain is truncated based on a technical criterion that the air volume design domain be located primarily between the gate drive IC device regions of the control PCB and the upper case frame plus cooler/power card stack. Such a strategy allows for the design of an optimal heat flow structure with shortest path between heat source and sink to logically minimize conductive thermal resistance. This design domain size reduction is further supported by the prior 2D design sensitivity study, where a heat flow structure spanning an excessively large area is shown to provide no added thermal benefit. The truncated design domain has the further feature of reducing the computational burden of the overall 3D optimization process.

Normalized thermal loads from Table 1, applied as heat flux, qa, BCs to the IC device cavities indicated in Fig. 9, are used in the optimization model. As shown in this figure, two boundary condition scenarios are investigated with the location of thermal ground varied in each case. In scenario 1, thermal ground is located at the end boundary of the cooler/power card stack, a surface normal to the plane of the control PCB. For scenario 2, a fixed temperature is assumed at the flat surface boundary to the upper case frame directly opposite from the IC devices.

The 3D heat flow structural optimization result for each scenario is shown in Fig. 10, where dark colored regions indicate solid (i.e., thermally conductive metal) material, and light regions represent void (i.e., nonconductive air). A 20% maximum solid material volume fraction constraint, vo = 0.2, with a filter radius, rf = 0.5 × 10−2, is used based on the 2D exploratory studies that identified these values in producing structural designs that consistently connect to all IC devices while using a small fraction of the available volumetric design domain. Using the SNOPT optimizer, solving for each design requires ∼12.5 h of computational time (for 1000 iterations) on a 40-core virtual machine with 2.60 GHz processors and 192 GB of RAM. For reference, a nearly identical scenario 1 structural optimization result (with a final objective function value within 1%) is obtained using the globally convergent method of moving asymptotes optimizer, although computational time is increased significantly to ∼4.5 days for an identical number of solution iterations.

Design Synthesis and Fabrication.

Implementing the design from scenario 2 is deemed feasible if the cast Al upper case frame is redesigned. However, the complex nonplanar surface of the upper case frame directly below the control PCB, Fig. 5(b), presents challenges in terms of establishing an effective contact area for TIM2, Fig. 6, if a 3D heat flow structural insert is instead utilized. Moreover, the upper case frame may be mechanically attached to a harsh environment secondary heat source (e.g., internal combustion engine, motor, or transaxle) under the hood. Thus, the structural concept from optimization scenario 1 is selected for design synthesis and fabrication of a standalone component added to the assembly since a planar interface opportunity with pressure and active temperature control exists at the end mating surface of the cooler/power card stack.

The complete design synthesis process for the scenario 1 postprocessed optimization result for a 3D heat flow structure in solid model form is shown in Fig. 11. In steps 1 and 2, respectively, the design domain is defined and the optimization result is obtained. In step 3, the optimization result is converted to stacked image data by slicing the optimized structure along the z-direction of the model in 5 × 10−4 m increments for approximately 200 sliced images using a custom Matlab® script interfaced with COMSOL®. This stacked image data is imported into a secondary commercial software tool [42] that is typically used for visualizing and segmenting medical images (such as computed tomography and magnetic resonance imaging data) to render a 3D computer-aided design solid model around the γ = 0.5 iso-surface, step 4. A fit check in the assembly model is then performed, step 5. Based on this initial computer-aided design solid model concept, a refined monolithic design, Fig. 11 step 6, is derived. The monolithic design has a unified planar surface for the TIM2 interface to the cooler/power card stack and an upper geometry for the TIM1 interface to the gate drive IC devices that is developed based on the optimization result for ease of manufacturing and further light-weighting. For preliminary inspection purposes, a detailed 3D printed rapid prototype concept model made of polylactic acid allows for a physical fit check with the upper case frame, Fig. 11 step 7.

To understand the anticipated temperature reduction effect for the gate drive IC devices, the numerical model described in Sec. 2 is updated to include the 3D heat flow structural design in as-optimized and refined monolithic forms. After a second grid refinement analysis, each final mesh consists of approximately 2.4 × 106 tetrahedral finite elements. Here, it is assumed that each part is fabricated out of Al with a thermal conductivity of 167 W/mK. For TIM1, a typical conformable thermal gap pad [43] of t = 1 mm thickness with a thermal conductivity, k = 0.8 W/mK, and dielectric breakdown voltage of 6 kV is conservatively assumed. A silver-filled thermal grease with a representative areal thermal resistance, Rth ∼ 6.2 × 10−5 m2K/W [44], is applied at the TIM2 interface. The PCB-to-ambient free convection coefficient at the corresponding inside case reference temperature from Table 1 is applied to all external surfaces of each newly added heat flow structure. The thermal contour results for the 3D heat flow structure in as-optimized versus monolithic form are shown in Fig. 12. The as-optimized structure has an average temperature of 66.3 °C, while the refined monolithic design has a slightly increased average temperature of 69.9 °C. The predicted IC device maximum, minimum, and average (of 14 IC devices) temperatures for the baseline and modified designs in Table 3 indicate an impactful 41 °C maximum and 31 °C average temperature reduction. Note that the results for the modified design are obtained using the monolithic 3D heat flow structure; thus, good performance is achieved with increased manufacturability considering conventional machining methods. Additionally, for the modified design with monolithic structure, the range of IC device temperatures, Tr, is reduced 48.6% from 37 °C in the baseline to 19 °C for the modified case. Hence, although the as-optimized structure could be additively manufactured using methods similar to those described in Refs. [40] and [45], a prototype monolithic structure is fabricated out of 6061-T6 alloy Al using traditional machining methods, Fig. 13(a), for performance verification by experiment.

For the experiments, a gate drive IC device control PCB is electrically modified such that select gate drive IC parasitic diodes are used as resistive element heaters. The advantage of this approach is that the conductive thermal resistance of the IC device package is correctly assessed in the physical experiments. Here, eight IC devices are selected and modified in the aforementioned fashion for the experiments; see the PCB bottom side view in Fig. 13(b) with chosen IC devices highlighted with red circles. The devices are electrically wired in parallel and connected to a 0–36 V, 0–6 A programmable direct current (DC) power supply (TDK-Lambda ZUP36-6). For temperature measurement, a calibrated fine wire Type K thermocouple (TC), ±2.2 ∘C accuracy is securely attached to the topside surface of each IC device using a 9.0 × 10−5 m thick Al foil tape (3M) affixed on the perimeter, away from the TC bead, with silicone adhesive. Device temperatures were recorded using a standard data acquisition (DAQ) system (National Instruments) connected to a computer.

Uncertainty Analysis.

The major sources of uncertainty in the experiments arise from the temperature measurement accuracy of the thermocouples and DAQ along with the accuracy of the power (i.e., applied voltage, Va, and measured current, I) from the DC power supply to the gate drive parasitic IC diodes. A summary of typical instrument accuracies is provided in Table 4. Note that the temperature measurement accuracy of the thermocouples and DAQ may be summed for a combined measurement accuracy of ±3.2 °C. A propagation of uncertainty analysis, per [46], then provides an overall uncertainty in the applied heater power of ±1.2% based on the instrument accuracy values in Table 4.

Experimental & Numerical Results.

In lieu of high temperature testing with a stacked liquid cooler plus active power card structure, a 12 V DC direct-to-air TEC, Laird Technologies, with 11 W cooling power is substituted to achieve the active temperature control boundary condition and an approximately uniform offset in the BC temperatures from Table 1. This test setup enables testing at an ambient, ∼ 22 °C, laboratory temperature; e.g., ΔTcooler = –50 ∘C down from 65 to ∼ 15 °C. The overlaid image in Fig. 13(c) shows the TEC and 3D heat flow structure assembly with a custom trimmed (filled-silicone polymer on rubber-coated fiberglass carrier) gap pad [43] (k = 0.8 W/mK, t = 0.001 m) applied at the TIM1 interface. A uniform thin layer of polysynthetic silver thermal compound (Arctic Silver 5) is precisely applied at the TIM2 interface. These TIMs are selected to reasonably represent the material conditions assumed in the prior computational models. However, to better characterize the effect of TIM1 on overall thermal performance of the system, an additional silicone-based material system with the same electrical breakdown voltage capability [47] is considered with ∼ 20× increase in thermal conductivity and a 50% reduction in thickness; i.e., k = 17 W/mK and t = 5 × 10−4 m.

Prior to evaluating the performance of the 3D heat flow control structure and its influence on gate drive IC device temperature, heat transfer experiments without active temperature control (i.e., the TEC) or 3D structure installed provide a baseline from which the temperature reduction effect is assessed. For the baseline test, the PCB is bolted to the upper case frame. All IC device temperature measurements are then taken at steady-state, which is achieved after applying power to the devices (approximately 1.23 W per device; 9.84 W total power) for a period of ten minutes. After evaluation of the baseline case, the 3D heat flow structure plus TEC assembly (with TIMs applied) is installed. Even compression of the TIM1 interface is achieved through uniform tightening of the bolts that mount the PCB to the upper case frame. After PCB installation, the experiment is repeated.

The IC device maximum, minimum, and average temperature results for all experimental cases are shown in a bar chart, Fig. 14. Observe that the gate drive IC device maximum and average temperatures are reduced significantly by 45.5 °C and 41.1 °C, respectively, using TIM1 with k = 0.8 W/mK and t = 0.001 m. The IC device temperature range, Tr, is also reduced by 41% from 14.7 °C in the baseline case to 8.7 °C for the modified design. Using the thinner and higher thermal conductivity (k = 17 W/mK, t = 5 × 10−4 m) TIM1 material, the IC device maximum and average temperatures are reduced even further by 60.0 °C and 55.0 °C, respectively, which indicates the importance of the TIM1 interface and material properties on enhancing performance. Additionally, using this second gap pad material, the IC device temperature range, Tr, is reduced 48% relative to the baseline case leading to highly uniform IC device temperatures.

For validation of the experiments, the simulations for the baseline and modified cases are once more updated to reflect the experimental conditions. Specifically, the power card heat loss is set to zero, the cooler temperature is fixed to the TEC condition of ∼ 15 °C, the internal/external convection heat transfer reference temperatures are set to the laboratory ambient of To = 22 °C, and gate drive IC device heat loss is assigned to the appropriate eight devices instead of all 14. Since the exact heat loss from the IC parasitic diodes is not known, the 1.23 W of power applied from the DC source to each device is uniformly scaled down (approximately 52%) in the baseline model to align with the experimentally measured results. These same scaled power loss values are then applied in the simulation with the 3D heat flow structure for straightforward comparison. Using this method, the IC device maximum, minimum, and average temperatures for both the baseline and modified cases are matched to within 5%; refer to the data in Table 3 for all cases. Thus, the experimental results are in satisfactory agreement with modeled predictions and confirm the effectiveness of the novel design approach in achieving significant IC device temperature reduction.

An optimal design methodology for three-dimensional heat flow structures for power electronics gate drive circuit PCB thermal management was described. A baseline thermal analysis of a representative power control unit was provided to understand the thermal challenges for high power density three-dimensional packaging of the control circuitry. A technology down-selection analysis of potential solutions was provided, and the structural optimization of a conductive heat flow structure was identified as a promising technical approach. Subsequently, a gradient-based structural optimization method was utilized to design a 3D heat flow structure within the existing empty air volume of the package. Two optimized heat flow control 3D structural designs were presented, and one of these designs was synthesized into a unique working prototype. Experiments with this prototype indicated a significant 45 °C gate drive IC device maximum temperature reduction effect in the laboratory environment, and corresponding simulations under high temperature ambient conditions anticipate an estimated 41 °C IC device maximum temperature reduction. The study also highlighted the importance of the thermophysical properties of the selected thermal interface material between the IC devices and 3D heat flow path. In summary, the experimental results are in line with the numerical predictions and indicate that the overall scientific method is highly effective in realizing enhanced thermal routing in three dimensions. Given the significant device temperature reductions that are achievable, the method is widely applicable not only to current Si-based electronics but also next-generation WBG systems including both active and passive components. These packaging techniques may be easily extend to other package geometries to enable further miniaturization and relevant increases in volumetric power density for future WBG electronics.

The authors would like to thank Hiroshi Ukegawa for his technical contributions to this project.

  • Cg =

    gate capacitance, F

  • f =

    switching frequency, Hz

  • h =

    convection coefficient, W/m2K

  • I =

    current, A

  • k =

    thermal conductivity, W/mK

  • L =

    junction channel length, m

  • p =

    penalization parameter

  • Pgd =

    gate driver power dissipation, W

  • q =

    heat flux, W/m2

  • Q =

    volumetric power density, W/m3

  • r =

    junction electrical resistance, Ohm

  • rf =

    filter radius

  • Rth =

    areal thermal resistance, m2K/W

  • t =

    thickness, m

  • T =

    temperature, ∘C

  • v =

    volume, m3

  • V =

    voltage, V

  • W =

    junction channel width, m

 Greek Symbols
  • Γ =

    boundary

  • γ =

    material design variable

  • Ω =

    domain

 Subscripts
  • a =

    applied

  • avg =

    average

  • c =

    convection

  • dd =

    supply

  • gs =

    gate-source

  • IC =

    integrated circuit

  • max =

    maximum

  • min =

    minimum

  • o =

    reference

  • r =

    range

  • t =

    threshold

Nozawa, N. , Maekawa, T. , Nozawa, S. , and Asakura, K. , 2009, “ Development of Power Control Unit for Compact-Class Vehicle,” SAE Int. J. Passeng. Cars - Electron. Electr. Syst., 2(1), pp. 376–382. [CrossRef]
Kubota, S. , Sakurai, T. , and Okada, H. , 2009, “ Size and Weight Reduction Technology for a Hybrid System,” SAE Int. J. Engines, 2(1), pp. 1143–1150. [CrossRef]
Kitazawa, O. , Kikuchi, T. , Nakashima, M. , Tomita, Y. , Kosugi, H. , and Kaneko, T. , 2016, “ Development of Power Control Unit for Compact-Class Vehicle,” SAE Int. J. Alt. Power, 5(2), pp. 278–285. [CrossRef]
Sakai, Y. , Ishiyama, H. , and Kikuchi, T. , 2007, “ Power Control Unit for High Power Hybrid System,” SAE Paper No. 2007-01-0271.
Ivanova, M. , Avenas, Y. , Schaeffer, C. , Dezord, J.-B. , and Schulz-Harder, J. , 2006, “ Heat Pipe Integrated in Direct Bonded Copper (DBC) Technology for Cooling of Power Electronics Packaging,” IEEE Trans. Power Electr., 21(6), pp. 1541–1547. [CrossRef]
Dede, E. M. , 2012, “ Optimization and Design of a Multipass Branching Microchannel Heat Sink for Electronics Cooling,” ASME J. Electron. Packag., 134(4), p. 041001. [CrossRef]
Zhou, F. , Liu, Y. , Liu, Y. , Joshi, S. N. , and Dede, E. M. , 2016, “ Modular Design for a Single-Phase Manifold Mini/Microchannel Cold Plate,” ASME J. Therm. Sci. Eng. Appl., 8(2), p. 021010. [CrossRef]
Waye, S. K. , Narumanchi, S. , Mihalic, M. , Moreno, G. , Bennion, K. , and Jeffers, J. , 2014, “ Advanced Liquid Cooling for a Traction Drive Inverter Using Jet Impingement and Microfinned Enhanced Surfaces,” 14th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Orlando, FL, May 27–30, pp. 1064–1074.
Wadsworth, D. , and Mudawar, I. , 1990, “ Cooling of a Multichip Electronic Module by Means of Confined Two-Dimensional Jets of Dielectric Liquid,” ASME J. Heat Transfer, 112(4), pp. 891–898. [CrossRef]
Joshi, S. N. , and Dede, E. M. , 2017, “ Two-Phase Jet Impingement Cooling for High Heat Flux Wide Band-Gap Devices Using Multi-Scale Porous Surfaces,” Appl. Therm. Eng., 110(5), pp. 10–17. [CrossRef]
Marz, M. , 2003, “ Thermal Management in High-Density Power Converters,” IEEE International Conference on Industrial Technology, Maribor, Slovenia, Dec. 10–12, pp. 1196–1201.
Johnson, R. W. , Evans, J. L. , Jacobsen, P. , Thompson, J. R. , and Christopher, M. , 2004, “ The Changing Automotive Environment: High-Temperature Electronics,” IEEE Trans. Electron. Packag. Manuf., 27(3), pp. 164–176.
Wrzecionko, B. , Bortis, D. , and Kolar, J. W. , 2014, “ A 120∘C Ambient Temperature Forced Air-Cooled Normally-Off SiC JFET Automotive Inverter System,” IEEE Trans. Power Electr., 29(5), pp. 2345–2358. [CrossRef]
Chu, R. C. , Simons, R. E. , Ellsworth, M. J. , Schmidt, R. R. , and Cozzolino, V. , 2004, “ Review of Cooling Technologies for Computer Products,” IEEE Trans. Device Mat. Reliab., 4(4), pp. 568–585. [CrossRef]
Integrated Circuit Division, 2017, “Aug. IXD_609 9-Ampere Low-Side Ultrafast MOSFET Drivers,” Integrated Circuit Division, Beverly, MA, accessed Sept. 19, 2018, http://www.ixysic.com/home/pdfs.nsf/www/IXD_609.pdf/$file/IXD_609.pdf
Steinberg, D. S. , 1991, Cooling Techniques for Electronic Equipment, 2nd ed., Wiley, New York.
Ferreira, B. , and Josifovic, I. , 2016, “ Passive Components for a 3D Environment,” International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM), Raleigh, NC, June 13–15.
Cossale, M. , Paredes, S. , Luijten, R. P. , and Michel, B. , 2015, “ Combined Power Delivery and Cooling for High Density, High Efficiency Microservers,” 21st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Paris, France, Sept. 30–Oct. 2, pp. 1–6.
Dunn, J. , 2004, “ Matching MOSFET Driver to MOSFETs,” Microchip Technology Inc., Chandler, AZ, accessed Sept. 19, 2018, http://ww1.microchip.com/downloads/en/AppNotes/00799b.pdf
Chen, Y. , Lee, F. C. , Amoroso, L. , and Wu, H.-P. , 2004, “ A Resonant MOSFET Gate Driver With Efficient Energy Recovery,” IEEE Trans. Power Electr., 19(2), pp. 470–477. [CrossRef]
Zhang, Z. , Li, F. F. , and Liu, Y. F. , 2014, “ A High-Frequency Dual-Channel Isolated Resonant Gate Driver With Low Gate Drive Loss for ZVS Full-Bridge Converters,” IEEE Trans. Power Electr., 29(6), pp. 3077–3090. [CrossRef]
Zhang, Z. , Eberle, W. , Yang, Z. , Liu, Y. F. , and Sen, P. C. , 2008, “ Optimal Design of Resonant Gate Driver for Buck Converter Based on a New Analytical Loss Model,” IEEE Trans. Power Electr., 23(2), pp. 653–666. [CrossRef]
Anthony, P. , McNeill, N. , and Holliday, D. , 2014, “ High-Speed Resonant Gate Driver With Controlled Peak Gate Voltage for Silicon Carbide MOSFETs,” IEEE Trans. Ind. Appl., 50(1), pp. 573–583. [CrossRef]
Moench, S. , Kallfass, I. , Reiner, R. , Weiss, B. , Waltereit, P. , Quay, R. , and Ambacher, O. , 2016, “ Single-Input GaN Gate Driver Based on Depletion-Mode Logic Integrated With a 600 V GaN-on-Si Power Transistor,” IEEE fourth Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Fayetteville, AR, Nov. 7–9, pp. 204–209.
Che, S. , Nagai, S. , Negoro, N. , Kawai, Y. , Tabata, O. , Enomoto, S. , Anda, Y. , and Hatsuda, T. , 2017, “ A1W Power Consumption GaN-Based Isolated Gate Driver for a 1.0 MHz GaN Power System,” 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, May 28–June 1, pp. 33–36.
Bendsoe, M. P. , and Sigmund, O. , 2003, Topology Optimization—Theory, Methods and Applications, 2nd ed., Springer, Berlin.
Dede, E. M. , Lee, J. , and Nomura, T. , 2014, Multiphysics Optimization: Electromechanical System Applications and Optimization, Springer, London.
Hamada, K. , Nagao, M. , Ajioka, M. , and Kawai, F. , 2015, “ SiC–Emerging Power Device Technology for Next-Generation Electrically Powered Environmentally Friendly Vehicles,” IEEE Trans. Electron Dev., 62(2), pp. 278–285. [CrossRef]
Toyota—USA Newsroom, 2017, “Nov. 2016–2017 Toyota Prius PCU On the WWW,” Toyota Motor Sales, U.S.A., Inc., Torrance, CA, accessed Apr. 19, 2017, http://toyotanews.pressroom.toyota.com/
ANSYS, Inc., 2016, “ ANSYS® Heat Transfer, Release 17.2,” ANSYS, Canonsburg, PA.
Reddy, J. N. , and Gartling, D. K. , 2000, The Finite Element Method in Heat Transfer and Fluid Dynamics, 2nd ed., CRC Press, Boca Raton, FL.
Incropera, F. P. , Dewitt, D. P. , Bergman, T. L. , and Lavine, A. S. , 2007, Introduction to Heat Transfer, 5th ed, Wiley, Hoboken, NJ.
Hull, D. , and Clyne, T. W. , 1995, An Introduction to Composite Materials, 2nd ed., Cambridge University Press, Cambridge, UK.
Sedra, A. S. , and Smith, K. C. , 2004, Microelectronic Circuits, 5th ed., Oxford University Press, New York.
Dede, E. M. , Schmalenberg, P. , Nomura, T. , and Ishigaki, M. , 2015, “ Design of Anisotropic Thermal Conductivity in Multilayer Printed Circuit Boards,” IEEE Compon. Packag. Manuf. Technol., 5(12), pp. 1763–1774. [CrossRef]
Lohan, D. J. , Dede, E. M. , and Allison, J. T. , 2016, “ Topology Optimization Formulations for Circuit Board Heat Spreader Design.,” AIAA Paper No. AIAA 2016-3669.
COMSOL AB, 2015, “ COMSOL Multiphysics ver. 5.2,” COMSOL AB, Stockholm, Sweden.
Rojas-Labanda, S. , and Stolpe, M. , 2015, “ Benchmarking Optimization Solvers for Structural Topology Optimization,” Struct. Multidisc. Optim., 52(3), pp. 527–547. [CrossRef]
Soprani, S. , Haertel, J. H. K. , Lazarov, B. S. , Sigmund, O. , and Engelbrecht, K. , 2016, “ A Design Approach for Integrating Thermoelectric Devices Using Topology Optimization,” Appl. Energy, 176, pp. 49–64. [CrossRef]
Dede, E. M. , Joshi, S. , and Zhou, F. , 2015, “ Topology Optimization, Additive Layer Manufacturing, and Experimental Testing of an Air-Cooled Heat Sink,” ASME J. Mech. Des., 137(11), p. 111403. [CrossRef]
Alexandersen, J. , Sigmund, O. , and Aage, N. , 2016, “ Large Scale Three-Dimensional Topology Optimisation of Heat Sinks Cooled by Natural Convection,” Int. J. Heat Mass Transfer, 100, pp. 876–891. [CrossRef]
Materialise NV, 2015, “ Mimics Research 18.0,” Materialise NV, Leuven, Belgium.
Bergquist—Thermal Materials, 2018, “(Gap Pad VO Soft On the WWW,” Henkel Electronics Materials, LLC, Chanhassen, MN, accessed Sept. 19, 2018, http://www.bergquistcompany.com/thermal_materials/gap_pad/gap-pad-VOSoft_properties.htm
Narumanchi, S. , Mihalic, M. , Kelly, K. , and Eesley, G. , 2008, “ Thermal Interface Materials for Power Electronics Applications,” 11th IEEE ITHERM Conference, Orlando, FL, May 28–31, pp. 395–404.
Gerstler, W. D. , and Erno, D. , 2017, “ Introduction of an Additively Manufactured Multi-Furcating Heat Exchanger,” 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Orlando, FL, May 30–June 2, pp. 624–633.
Kline, S. J. , and McClintock, F. A. , 1953, “ Describing Uncertainties in Single-Sample Experiments,” Mech. Eng., 75(1), pp. 3–8.
Marian—Material Data Sheets, 2017, “Nov. Thermal Gap Filler Material On the WWW,” Marian Inc., Indianapolis, IN, accessed Sept. 19, 2018, http://www.marianinc.com/wp-content/uploads/2016/07/PS-1917-17W-hyper-soft-gap-filler.pdf
Copyright © 2019 by ASME
View article in PDF format.

References

Nozawa, N. , Maekawa, T. , Nozawa, S. , and Asakura, K. , 2009, “ Development of Power Control Unit for Compact-Class Vehicle,” SAE Int. J. Passeng. Cars - Electron. Electr. Syst., 2(1), pp. 376–382. [CrossRef]
Kubota, S. , Sakurai, T. , and Okada, H. , 2009, “ Size and Weight Reduction Technology for a Hybrid System,” SAE Int. J. Engines, 2(1), pp. 1143–1150. [CrossRef]
Kitazawa, O. , Kikuchi, T. , Nakashima, M. , Tomita, Y. , Kosugi, H. , and Kaneko, T. , 2016, “ Development of Power Control Unit for Compact-Class Vehicle,” SAE Int. J. Alt. Power, 5(2), pp. 278–285. [CrossRef]
Sakai, Y. , Ishiyama, H. , and Kikuchi, T. , 2007, “ Power Control Unit for High Power Hybrid System,” SAE Paper No. 2007-01-0271.
Ivanova, M. , Avenas, Y. , Schaeffer, C. , Dezord, J.-B. , and Schulz-Harder, J. , 2006, “ Heat Pipe Integrated in Direct Bonded Copper (DBC) Technology for Cooling of Power Electronics Packaging,” IEEE Trans. Power Electr., 21(6), pp. 1541–1547. [CrossRef]
Dede, E. M. , 2012, “ Optimization and Design of a Multipass Branching Microchannel Heat Sink for Electronics Cooling,” ASME J. Electron. Packag., 134(4), p. 041001. [CrossRef]
Zhou, F. , Liu, Y. , Liu, Y. , Joshi, S. N. , and Dede, E. M. , 2016, “ Modular Design for a Single-Phase Manifold Mini/Microchannel Cold Plate,” ASME J. Therm. Sci. Eng. Appl., 8(2), p. 021010. [CrossRef]
Waye, S. K. , Narumanchi, S. , Mihalic, M. , Moreno, G. , Bennion, K. , and Jeffers, J. , 2014, “ Advanced Liquid Cooling for a Traction Drive Inverter Using Jet Impingement and Microfinned Enhanced Surfaces,” 14th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Orlando, FL, May 27–30, pp. 1064–1074.
Wadsworth, D. , and Mudawar, I. , 1990, “ Cooling of a Multichip Electronic Module by Means of Confined Two-Dimensional Jets of Dielectric Liquid,” ASME J. Heat Transfer, 112(4), pp. 891–898. [CrossRef]
Joshi, S. N. , and Dede, E. M. , 2017, “ Two-Phase Jet Impingement Cooling for High Heat Flux Wide Band-Gap Devices Using Multi-Scale Porous Surfaces,” Appl. Therm. Eng., 110(5), pp. 10–17. [CrossRef]
Marz, M. , 2003, “ Thermal Management in High-Density Power Converters,” IEEE International Conference on Industrial Technology, Maribor, Slovenia, Dec. 10–12, pp. 1196–1201.
Johnson, R. W. , Evans, J. L. , Jacobsen, P. , Thompson, J. R. , and Christopher, M. , 2004, “ The Changing Automotive Environment: High-Temperature Electronics,” IEEE Trans. Electron. Packag. Manuf., 27(3), pp. 164–176.
Wrzecionko, B. , Bortis, D. , and Kolar, J. W. , 2014, “ A 120∘C Ambient Temperature Forced Air-Cooled Normally-Off SiC JFET Automotive Inverter System,” IEEE Trans. Power Electr., 29(5), pp. 2345–2358. [CrossRef]
Chu, R. C. , Simons, R. E. , Ellsworth, M. J. , Schmidt, R. R. , and Cozzolino, V. , 2004, “ Review of Cooling Technologies for Computer Products,” IEEE Trans. Device Mat. Reliab., 4(4), pp. 568–585. [CrossRef]
Integrated Circuit Division, 2017, “Aug. IXD_609 9-Ampere Low-Side Ultrafast MOSFET Drivers,” Integrated Circuit Division, Beverly, MA, accessed Sept. 19, 2018, http://www.ixysic.com/home/pdfs.nsf/www/IXD_609.pdf/$file/IXD_609.pdf
Steinberg, D. S. , 1991, Cooling Techniques for Electronic Equipment, 2nd ed., Wiley, New York.
Ferreira, B. , and Josifovic, I. , 2016, “ Passive Components for a 3D Environment,” International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM), Raleigh, NC, June 13–15.
Cossale, M. , Paredes, S. , Luijten, R. P. , and Michel, B. , 2015, “ Combined Power Delivery and Cooling for High Density, High Efficiency Microservers,” 21st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Paris, France, Sept. 30–Oct. 2, pp. 1–6.
Dunn, J. , 2004, “ Matching MOSFET Driver to MOSFETs,” Microchip Technology Inc., Chandler, AZ, accessed Sept. 19, 2018, http://ww1.microchip.com/downloads/en/AppNotes/00799b.pdf
Chen, Y. , Lee, F. C. , Amoroso, L. , and Wu, H.-P. , 2004, “ A Resonant MOSFET Gate Driver With Efficient Energy Recovery,” IEEE Trans. Power Electr., 19(2), pp. 470–477. [CrossRef]
Zhang, Z. , Li, F. F. , and Liu, Y. F. , 2014, “ A High-Frequency Dual-Channel Isolated Resonant Gate Driver With Low Gate Drive Loss for ZVS Full-Bridge Converters,” IEEE Trans. Power Electr., 29(6), pp. 3077–3090. [CrossRef]
Zhang, Z. , Eberle, W. , Yang, Z. , Liu, Y. F. , and Sen, P. C. , 2008, “ Optimal Design of Resonant Gate Driver for Buck Converter Based on a New Analytical Loss Model,” IEEE Trans. Power Electr., 23(2), pp. 653–666. [CrossRef]
Anthony, P. , McNeill, N. , and Holliday, D. , 2014, “ High-Speed Resonant Gate Driver With Controlled Peak Gate Voltage for Silicon Carbide MOSFETs,” IEEE Trans. Ind. Appl., 50(1), pp. 573–583. [CrossRef]
Moench, S. , Kallfass, I. , Reiner, R. , Weiss, B. , Waltereit, P. , Quay, R. , and Ambacher, O. , 2016, “ Single-Input GaN Gate Driver Based on Depletion-Mode Logic Integrated With a 600 V GaN-on-Si Power Transistor,” IEEE fourth Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Fayetteville, AR, Nov. 7–9, pp. 204–209.
Che, S. , Nagai, S. , Negoro, N. , Kawai, Y. , Tabata, O. , Enomoto, S. , Anda, Y. , and Hatsuda, T. , 2017, “ A1W Power Consumption GaN-Based Isolated Gate Driver for a 1.0 MHz GaN Power System,” 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, May 28–June 1, pp. 33–36.
Bendsoe, M. P. , and Sigmund, O. , 2003, Topology Optimization—Theory, Methods and Applications, 2nd ed., Springer, Berlin.
Dede, E. M. , Lee, J. , and Nomura, T. , 2014, Multiphysics Optimization: Electromechanical System Applications and Optimization, Springer, London.
Hamada, K. , Nagao, M. , Ajioka, M. , and Kawai, F. , 2015, “ SiC–Emerging Power Device Technology for Next-Generation Electrically Powered Environmentally Friendly Vehicles,” IEEE Trans. Electron Dev., 62(2), pp. 278–285. [CrossRef]
Toyota—USA Newsroom, 2017, “Nov. 2016–2017 Toyota Prius PCU On the WWW,” Toyota Motor Sales, U.S.A., Inc., Torrance, CA, accessed Apr. 19, 2017, http://toyotanews.pressroom.toyota.com/
ANSYS, Inc., 2016, “ ANSYS® Heat Transfer, Release 17.2,” ANSYS, Canonsburg, PA.
Reddy, J. N. , and Gartling, D. K. , 2000, The Finite Element Method in Heat Transfer and Fluid Dynamics, 2nd ed., CRC Press, Boca Raton, FL.
Incropera, F. P. , Dewitt, D. P. , Bergman, T. L. , and Lavine, A. S. , 2007, Introduction to Heat Transfer, 5th ed, Wiley, Hoboken, NJ.
Hull, D. , and Clyne, T. W. , 1995, An Introduction to Composite Materials, 2nd ed., Cambridge University Press, Cambridge, UK.
Sedra, A. S. , and Smith, K. C. , 2004, Microelectronic Circuits, 5th ed., Oxford University Press, New York.
Dede, E. M. , Schmalenberg, P. , Nomura, T. , and Ishigaki, M. , 2015, “ Design of Anisotropic Thermal Conductivity in Multilayer Printed Circuit Boards,” IEEE Compon. Packag. Manuf. Technol., 5(12), pp. 1763–1774. [CrossRef]
Lohan, D. J. , Dede, E. M. , and Allison, J. T. , 2016, “ Topology Optimization Formulations for Circuit Board Heat Spreader Design.,” AIAA Paper No. AIAA 2016-3669.
COMSOL AB, 2015, “ COMSOL Multiphysics ver. 5.2,” COMSOL AB, Stockholm, Sweden.
Rojas-Labanda, S. , and Stolpe, M. , 2015, “ Benchmarking Optimization Solvers for Structural Topology Optimization,” Struct. Multidisc. Optim., 52(3), pp. 527–547. [CrossRef]
Soprani, S. , Haertel, J. H. K. , Lazarov, B. S. , Sigmund, O. , and Engelbrecht, K. , 2016, “ A Design Approach for Integrating Thermoelectric Devices Using Topology Optimization,” Appl. Energy, 176, pp. 49–64. [CrossRef]
Dede, E. M. , Joshi, S. , and Zhou, F. , 2015, “ Topology Optimization, Additive Layer Manufacturing, and Experimental Testing of an Air-Cooled Heat Sink,” ASME J. Mech. Des., 137(11), p. 111403. [CrossRef]
Alexandersen, J. , Sigmund, O. , and Aage, N. , 2016, “ Large Scale Three-Dimensional Topology Optimisation of Heat Sinks Cooled by Natural Convection,” Int. J. Heat Mass Transfer, 100, pp. 876–891. [CrossRef]
Materialise NV, 2015, “ Mimics Research 18.0,” Materialise NV, Leuven, Belgium.
Bergquist—Thermal Materials, 2018, “(Gap Pad VO Soft On the WWW,” Henkel Electronics Materials, LLC, Chanhassen, MN, accessed Sept. 19, 2018, http://www.bergquistcompany.com/thermal_materials/gap_pad/gap-pad-VOSoft_properties.htm
Narumanchi, S. , Mihalic, M. , Kelly, K. , and Eesley, G. , 2008, “ Thermal Interface Materials for Power Electronics Applications,” 11th IEEE ITHERM Conference, Orlando, FL, May 28–31, pp. 395–404.
Gerstler, W. D. , and Erno, D. , 2017, “ Introduction of an Additively Manufactured Multi-Furcating Heat Exchanger,” 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Orlando, FL, May 30–June 2, pp. 624–633.
Kline, S. J. , and McClintock, F. A. , 1953, “ Describing Uncertainties in Single-Sample Experiments,” Mech. Eng., 75(1), pp. 3–8.
Marian—Material Data Sheets, 2017, “Nov. Thermal Gap Filler Material On the WWW,” Marian Inc., Indianapolis, IN, accessed Sept. 19, 2018, http://www.marianinc.com/wp-content/uploads/2016/07/PS-1917-17W-hyper-soft-gap-filler.pdf

Figures

Grahic Jump Location
Fig. 1

Typical configuration of gate driver

Grahic Jump Location
Fig. 2

Power control unit downsizing image and goal. (Reprinted with permission from Hamada et al. [28]. Copyright 2015 by IEEE).

Grahic Jump Location
Fig. 3

Cutaway view of a representative PCU; adapted with permission from Ref. [29]

Grahic Jump Location
Fig. 4

Solid model geometry for computational analysis: (a) isometric view, (b) top view with PCB transparent for clarity — red-dashed boxes indicate gate drive IC device locations, and (c) section view of stacked cooler with control PCB directly above

Grahic Jump Location
Fig. 5

Thermal contour results for baseline numerical model: (a) control PCB with upper case frame shown transparent and inner power card stack plus cooler hidden, for clarity, and (b) upper case frame only

Grahic Jump Location
Fig. 6

Cross section schematic of design region and concept for 3D heat flow structure

Grahic Jump Location
Fig. 7

Loads and BCs for 2D optimization study

Grahic Jump Location
Fig. 8

Pareto front of material fraction design sensitivity. Note: for inset images, dark regions = thermally conductive (i.e., solid) material; light regions = nonthermally conductive material (i.e., void).

Grahic Jump Location
Fig. 9

Extracted air volume 3D design domain

Grahic Jump Location
Fig. 10

Three-dimensional heat flow structure optimization results. Note: dark regions = thermally conductive (i.e., solid) material; light regions = nonthermally conductive material (i.e., void).

Grahic Jump Location
Fig. 11

Design synthesis process from optimization result to rapid prototype

Grahic Jump Location
Fig. 12

Thermal contour results comparing performance of 3D heat flow structure in as-optimized, (a), versus monolithic (b), form

Grahic Jump Location
Fig. 13

Experimental setup: (a) prototype Al 3D heat flow structure; (b) control PCB bottom side view—red circled IC devices are powered, and (c) PCB mounted into upper case frame with overlaid view of TEC plus 3D heat flow structure assembly including TIMs (mounted between PCB and case)

Grahic Jump Location
Fig. 14

Experimental results for IC device maximum, minimum, and average temperature measurements

Tables

Table Grahic Jump Location
Table 1 Assumed model loads, BCs, and material properties
Table Grahic Jump Location
Table 2 Technology performance comparison
Table Grahic Jump Location
Table 3 Numerically predicted and experimentally measured results
Table Footer NoteNote: Sim. = simulation; Exp. = experimental.
Table Footer NoteaResult using Table 1 conditions.
Table Footer NotebTIM1: k = 0.8 W/mK; t = 1 mm.
Table Footer NotecResult using experimental conditions.
Table Footer NotedTIM1: k = 17 W/mK; t = 0.5 mm.
Table Grahic Jump Location
Table 4 List of instrument accuracies

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